The present invention relates to stacked microelectronic assemblies and methods of making such assemblies, to methods of forming such assemblies and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package, which in turn is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip chip” designs, the front face of the chip confronts the face of the circuit panel and the contacts on the chip are bonded directly to the circuit panel by solder balls or other connecting elements. The “flip chip” design provides a relatively compact planar arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip front face. However, this approach suffers from cost and reliability problems. As disclosed, for example, in certain embodiments of commonly assigned U.S. Pat. Nos. 5,148,265 5,148,266, and 5,679,977 the disclosures of which are incorporated herein by reference certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip chip bonding without the reliability and testing problems commonly encountered in that approach. A Package which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself are commonly referred to as “chip size packages”.
Besides minimizing the planar area of the circuit panel occupied by a microelectronic assembly, it is also desirable to produce a chip package that presents a low overall height or dimension perpendicular to the plane of the circuit panel. Such thin microelectronic packages allow for placement of a circuit panel having the packages mounted thereon in close proximity to neighboring structures, thus reducing the overall size of the product incorporating the circuit panel.
Various proposals have been advanced for providing plural chips in a single package or module. In a conventional “multi-chip module”, the chips are mounted side-by-side on a single package substrate, which in turn can be mounted to the circuit panel. This approach offers only limited reduction in the aggregate area of the circuit panel occupied by the chips. The aggregate area is still greater than the total surface area of the individual chips in the module. It has also been proposed to package plural chips in a “stacked” arrangement, i.e., an arrangement where plural chips are placed one on top of another. In a stacked arrangement, several chips can be mounted in an area of the circuit panel that is less than the total area of the chips. Certain stacked chip arrangements are disclosed, for example, in certain embodiments of the aforementioned '977 and '265 patents and in U.S. Pat. No. 5,347,159, the disclosure of which is incorporated herein by reference. U.S. Pat. No. 4,941,033, also incorporated herein by reference, discloses an arrangement in which chips are stacked on top of another and interconnected with one another by conductors on so-called “wiring films” associated with the chips.
Another approach is presented in commonly assigned U.S. Pat. Nos. 6,121,676; 6,225,688; and U.S. patent application Ser. No. 09/776,356 filed Feb. 2, 2001, the disclosures of which are incorporated herein by reference. The stacked microelectronic assemblies disclosed certain preferred embodiments of these patents and application include a flexible substrate having a plurality of attachment sites and conductive elements and a plurality of chips connected thereto. The flexible substrate is folded so as to stack the chips in substantially vertical alignment with one another. The resulting stacked assemblies typically have at least one layer of flexible substrate for every one or two chips in the stack which adds to the overall thickness of the assembly.
Certain preferred embodiments of U.S. Pat. No. 5,861,666, the disclosure of which is incorporated herein by reference, disclose an assembly of plural chip-bearing units vertically stacked one atop the other. Each unit includes a small panel or “interposer” and a semiconductor chip mounted thereto. The assembly also includes compliant layers disposed between the chips and the interposers so as to permit relative movement of the chips and interposers to compensate for thermal expansion and contraction of the components. The units are stacked so that the chips overlie one another, and are electrically interconnected with one another as, for example, by solder balls connecting conductive features of adjacent interposers to one another. The presence of an interposer in each unit contributes to the thickness of the stack.
Still further improvements in stacked chip assemblies would be desirable. Stacked chip assemblies should deal effectively with the problems associated with heat generation in stacked chips. Chips dissipate electrical power as heat during operation. Where chips are stacked one atop the other, it is difficult to dissipate the heat generated by the chips in the middle of the stack. Also, chips and circuit panels undergo substantial thermal expansion and contraction during operation. Differences in thermal expansion and contraction can impose significant mechanical strain on elements of the assembly, including the electrical connections. Moreover, the assembly should be simple, reliable and easily fabricated in a cost-effective manner.